module video_timming_detect(
	// input
	input rst_n,
	input clk,
	input hsync,
	input vsync,
	input data_enable,
	input second,
	// output
	output [15:0] h_total,
	output [15:0] v_total,
	output [15:0] h_sync,
	output [15:0] h_sync_back,
	output [15:0] h_sync_back_active,
	output [15:0] v_sync,
	output [15:0] v_sync_back,
	output [15:0] v_sync_back_active,
	output [31:0] total_pixel
);

reg [15:0] h_total_reg;
reg [15:0] v_total_reg;
reg [15:0] h_sync_reg;
reg [15:0] h_sync_back_reg;
reg [15:0] h_sync_back_active_reg;
reg [15:0] v_sync_reg;
reg [15:0] v_sync_back_reg;
reg [15:0] v_sync_back_active_reg;
reg [31:0] total_pixel_reg;

assign h_total = h_total_reg;
assign v_total = v_total_reg;
assign h_sync = h_sync_reg;
assign h_sync_back = h_sync_back_reg;
assign h_sync_back_active = h_sync_back_active_reg;
assign v_sync = v_sync_reg;
assign v_sync_back = v_sync_back_reg;
assign v_sync_back_active_back = v_sync_back_active_reg;
assign total_pixel = total_pixel_reg;


reg [31:0] total_pixel_count;
reg [15:0] line_count;
reg [15:0] line_pixel_count;
reg prev_second;
reg prev_hsync;
reg prev_vsync;


always @ (posedge clk)
begin
	if(!rst_n) begin
		total_pixel_count <= 0;
		h_total_reg <= 0;
		v_total_reg <= 0;
		h_sync_reg <= 0;
		h_sync_back_reg <= 0;
		h_sync_back_active_reg <= 0;
		v_sync_reg <= 0;
		v_sync_back_reg <= 0;
		v_sync_back_active_reg <= 0;
		total_pixel_reg <= 0;
		line_count <= 0;
		line_pixel_count <= 0;
		prev_second <= 0;
		prev_hsync <= 0;
		prev_vsync <= 0;
	end
	else begin
	
		// total_pixel_count
		prev_second <= second;
		if((!prev_vsync) & vsync ) begin
			total_pixel_reg <= total_pixel_count;
			total_pixel_count <= 0;
		end
		else begin
			total_pixel_count <= total_pixel_count+1;
		end
		
		// h_total_reg
		prev_hsync <= hsync;
		if((!prev_hsync) & hsync ) begin
			h_total_reg <= line_pixel_count;
			line_pixel_count <= 0;
			line_count <= line_count+1;
			
		end
		else begin
			line_pixel_count <= line_pixel_count+1;
		end
		
		// v_total_reg
		prev_vsync <= vsync;
		if((!prev_vsync) & vsync ) begin
			v_total_reg <= line_count;
			line_count <= 0;
		end
	end	
end

endmodule